• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a memory device comprising: a memory matrix with intersection points (100); a current supply circuit (302) adapted to supply a programming current (IWL) to a selected row conductor track of the array during a programming operation to change the resistive state of a selected memory cell coupled between selected row conductor track and a selected column conductor track; a leakage current detection circuit (304) coupled to the column conductor tracks (104) except for the selected column conductor track adapted to detect leakage currents during the programming operation; and a current limit generating circuit (308) adapted to generate a current limit (IL) based on the sum of the leakage currents and a reference current (IREF), and to provide the current limit to the power supply circuit (302) for limiting the programming current.
    公开号:FR3042304A1
    申请号:FR1559648
    申请日:2015-10-09
    公开日:2017-04-14
    发明作者:Alexandre Levisse
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    METHOD AND CIRCUIT FOR CONTROLLING PROGRAMMING CURRENT IN NON-VOLATILE MEMORY MATRIX
    Field
    The present description relates to the field of nonvolatile memories, and in particular a method and a circuit for controlling the programming current of nonvolatile memory cells in a memory matrix with intersection points (memory also known by the English name of memory "cross-section"). Statement of Prior Art
    It has already been proposed to use programmable resistive elements in memory cells to ensure nonvolatile data storage. Such resistive elements are programmable to take one of a plurality of different resistive states. The programmed resistive state is maintained when the supply voltage of the memory cell is disconnected, and thus data can be stored in a non-volatile manner.
    Various types of resistive elements have been proposed, some of which can be programmed by the direction and / or the level of current that is passed through the element. Examples of such current-programmable resistive elements include OxRAM (Oxygen Random Access Memory), PC-RAMs (Phase Change Random Access Memory). ) and MRAM (Magnetic RAM) using, for example, STT technology (SPIN transfer torque).
    In order to obtain a compact memory array, it has been proposed to incorporate nonvolatile memory cells in a memory matrix architecture with points of intersection. In such a matrix, memory cells are arranged in rows and columns, each row having an associated row conductive track, and each column having an associated column conductive track. Each memory cell comprises a programmable resistive element coupled between a corresponding row of conductive track and a corresponding column conductor track. Thus, by applying particular voltage levels to the column and row conductive tracks, a memory cell may be selected from the array for a read or write operation.
    Depending on the particular technology of the nonvolatile programmable resistive element, the level of the programming current used during the programming operation may affect some property of the programmed resistive state, such as the programmed resistor and / or the duration of the programmed resistive state. retention of the data.
    For example, in the case of an OxRAM memory cell, when going from the high resistive state to the low resistive state, the programming current will rise rapidly and the level reached by the programming current will determine the level. programmed resistance of the cell. Therefore, in order to program a particular desired resistance, the current should be limited during the programming operation.
    However, a difficulty in the intersection point memory arrays is that, while a given memory cell is being programmed, a certain amount of the current sent into the array will be lost by leakage of current into cells. memories not selected. Such current paths are known in the art as stealth paths (sneak path). The amount of current flowing through stealthy paths will depend on various factors, such as the resistive states of the unselected memory cells, the position of the selected memory cell in the array, the operating conditions, the age of the device, and the performance of the device. other components in each memory cell. There is therefore a technical problem to appropriately compensate for such leakage currents.
    Thus, there is a need in the art for a circuit and method providing effective current limiting during programming operations in a nonvolatile point-of-intersection memory array. summary
    An object of embodiments of the present disclosure is to at least partially solve one or more needs of the prior art.
    According to one aspect, there is provided a memory device comprising: an intersection point memory array comprising a plurality of row conductive tracks, a plurality of column conductive tracks and a plurality of memory cells arranged in rows and columns, each cell memory comprising a nonvolatile programmable resistive element coupled between a corresponding one of the row conductive tracks and a corresponding one of the column conductive tracks; a current supply circuit adapted to supply a programming current to one of the row conductor tracks during a programming operation to change the resistive state of a selected memory cell coupled between the selected row conductor track and one of the column conductive tracks selected; a leakage current detection circuit coupled to the plurality of column conductor tracks except for the selected column conductor track adapted to detect leakage currents during the programming operation; and a current limit generating circuit adapted to generate a current limit based on the sum of the leakage currents and a reference current, and to provide the current limit to the current supply circuit to limit the programming current.
    According to one embodiment, the current limit generating circuit is adapted to generate the current limit by adding the sum of the leakage currents to the reference current, the reference current representing the programming current to be applied to the memory cell. selected.
    In one embodiment, the power supply circuit includes a voltage regulator for controlling a first voltage level applied to the selected row conductor track.
    According to one embodiment, the voltage regulator comprises a first transistor coupled to the selected row conductor track and having its control node coupled to the output of a comparator adapted to compare the voltage on the selected row conductor track to a selected one. reference voltage equal to the first voltage level.
    According to one embodiment, the power supply circuit comprises a current mirror having a reference branch coupled to receive the current limit and another branch coupled to the selected row conductor track.
    According to one embodiment, the power supply circuit comprises another comparator adapted to compare a first voltage level generated on the basis of the current limit with a second voltage level generated on the basis of the programming current, and to control the programming current based on the comparison.
    In one embodiment, the leakage current detection circuit includes a voltage regulator for controlling a second voltage level applied to the column conductor tracks except for the selected column conductor track.
    According to one embodiment, the current limit generation circuit comprises: a first current mirror having a reference branch coupled to receive the sum of the leakage currents, and another branch; a second current mirror having a reference branch coupled to receive the reference current, and another branch, the other branches of the first and second current mirrors coupled to an output line of the current limit generating circuit providing the current limit.
    According to one embodiment, the memory device comprises: one or more other power supply circuitry adapted to supply a programming current to one or more other row conductor traces selected during the programming operation to change the resistive state one or more of the memory cells coupled to the selected column conductor track; and a dividing circuit adapted to divide the sum of the leakage currents by the number of current supply circuits.
    According to one embodiment, the nonvolatile programmable resistive element is selected from an OxRAM (Oxide Random Access Memory) device, a PCM (Phase Change Memory) device, and an MRAM (Magnetic RAM) device.
    According to one embodiment, each memory cell further comprises a bidirectional selection device coupled in series with the non-volatile programmable resistive element and adapted to conduct above a voltage threshold.
    According to another aspect, there is provided a method for limiting a programming current in an intersection point nonvolatile memory array comprising a plurality of row conductor tracks, a plurality of column conductor tracks, and a plurality of memory cells arranged in accordance with the present invention. rows and columns, each memory cell comprising a non-volatile programmable resistive element coupled between a corresponding one of the row conductor tracks and a corresponding one of the column conductor tracks, the method comprising: providing, by a power supply circuit, current, a programming current at a selected one of the row conductive tracks during a programming operation to change the resistive state of a selected memory cell coupled between the selected row conductive track and a selected one of the conductive tracks of column ; detecting, by a leakage current detection circuit coupled to the plurality of column conductor tracks except for the selected column conductor track, leakage currents during the programming operation; generating, by a current limit generating circuit, a current limit based on the sum of the leakage currents and a reference current; and supplying the current limit to the power supply circuit to limit the programming current.
    Brief description of the drawings
    The foregoing and other features and advantages will become apparent with the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings in which: FIG. 1A schematically illustrates a dot memory array intersection according to an exemplary embodiment; Fig. 1B schematically illustrates a nonvolatile memory cell of the matrix of Fig. 1A in more detail according to an exemplary embodiment; FIG. 2 is a graph showing a current-voltage relationship across the memory cell of FIG. 1B according to an exemplary embodiment; FIG. 3 schematically illustrates a memory device provided with a current limiting circuit according to an exemplary embodiment of the present description; FIG. 4 schematically illustrates a memory device provided with a current limiting circuit according to another embodiment of the present description; FIG. 5 is a flowchart illustrating steps in a method of limiting a programming current in a non-volatile memory cell according to an example embodiment of the present description; FIG. 6 diagrammatically illustrates the memory device of FIG. 3 in more detail according to an exemplary embodiment; Figure 7 schematically illustrates the memory device of Figure 3 in more detail according to another embodiment; FIG. 8 schematically illustrates a memory device provided with a current limiting circuit according to another exemplary embodiment in which several memory cells can be programmed at a time; and Figure 9 schematically illustrates the memory device of Figure 8 in more detail according to an exemplary embodiment.
    detailed description
    In the present description, the term "connected" is used to denote a direct electrical connection between two elements, while the term "coupled" is used to designate an electrical connection between two elements which may be direct, or which may be via one or more components such as resistors, capacitors, or transistors. In addition, as used herein, the term "around" is used to refer to a range of ± 10% around the value in question.
    As used herein, the term "column conductive track" is used to refer to the vertically drawn conductive traces of a memory array in the figures, while the term "row conductive track" is used to denote the tracks. conductors of the memory array drawn horizontally in the figures. It will be apparent to those skilled in the art that in practice row conductor tracks and column conductor tracks could have any orientation.
    FIG. 1A schematically illustrates an example of an intersection point memory matrix 100 according to an exemplary embodiment. As illustrated, the array 100 includes, for example, row conductive paths 102 and column conductive tracks 104. In the example of Fig. 1A, the array comprises four row conductive tracks and four column conductive tracks, although that in alternative embodiments there may be any number of row conductive tracks and any number of column conductive tracks, where n and m are both, for example, integers equal to or greater than two.
    The memory array 100 comprises memory cells 106 arranged in rows and columns, a row of memory cells for each row conducting track, and a memory cell column for each column conducting track. Each memory cell is coupled between a corresponding row conductor track 102 and a corresponding column conductor track 104. For example, the memory cells in the left side column of the array all have a terminal coupled to the column conductive track 104 of the matrix. left side, and their other terminals coupled to the corresponding row 102 conductive tracks.
    A memory cell of the array may be selected during a read or write operation by applying appropriate voltages to row and column conductive tracks to pass a current through the selected memory cell. An example is shown in FIG. 1A in which, during a write operation, a memory cell in the upper left corner of the array is selected by applying a select voltage Vsel to the upper row conductive track 102 and a low voltage Vb to the conductive column track 104 on the left. Thus, the upper left memory cell of the matrix has a voltage of Vsel-Vb at its terminals. For example, Vsel is at approximately the supply voltage VDDH of the circuit, which is for example in the range of 1 to 3 V, and Vb is at 0 V or around this value. For example, a current applied to a memory cell selected from the row conductor track to the column conductive track causes the resistive element to be switched from a high resistance state to a low resistance state. To program the resistive element to assume a different resistance state, a current is for example applied from the column conductor track to the row conductor track of the memory cell, or a different current level is applied.
    The other row conductive tracks 102 have a voltage Vx applied to them, and the other column conductor tracks have a voltage Vsel-Vx applied thereto. The memory cells 106 each comprise, for example, a bidirectional selection device, described in greater detail below, which is a non-linear device associated with a threshold level Vt. The threshold level Vt is for example less than Vx. When the voltage at the terminals of the selection device is greater than the threshold level Vt, the selection device provides a path of relatively low resistance, allowing the passage of a relatively high current therein. When the voltage at the terminals of the selection device is lower than the threshold voltage Vt, the selection device has a relatively high resistance path, so that the current flowing in it is relatively low, this current corresponding to a current leak. The sum of these leakage currents flowing in multiple stealth paths in the array, corresponding to the unselected memory cells, may be significant, and therefore it is desirable to provide compensation for these leakage currents.
    The level of Vx is chosen to be between Vb and Vsel. For example, Vx is equal to or between Vsel / 2 and Vsel / 3. In the case where Vx = Vsel / 2 and Vb = 0 V, the voltage across the memory cells in the left column of the matrix and in the upper row of the matrix will be equal to Vsel / 2, and the voltage at The terminals of all the other memory cells of the matrix will be 0 V. In the case where Vx = Vsel / 3 and Vb = 0 V, the voltage across all the memory cells in the matrix, except the memory cell being in the upper left corner, will be Vsel / 3. For example, the level of the voltage Vx is chosen so as to minimize the leakage current in the matrix, and generally for most matrix sizes, a Vsel / 2 level works well.
    Most of the current resulting from voltage levels Vsel and Vb will pass through the selected memory cell. However, as mentioned above, part of the current will be lost due to the leakage of current by the stealth paths in the memory cells passing through other unselected memory cells. For example, when the voltage Vsel is applied to the upper row conductive track 102 of the matrix, a programming current Ip will flow in the upper left memory cell and leakage currents (In, Ιχ2 and I13) can flow. through the other memory cells in the upper row of the array, depending on the voltage level Vsel-Vx. These leakage currents will reduce the programming current Ip passing through the selected memory cell.
    FIG. 1B illustrates the example of the memory cell 106 of the matrix of FIG. 1Ά according to an exemplary embodiment. Each memory cell 106 comprises, for example, a programmable resistive element 108 coupled in series with a bidirectional selection device 110.
    The programmable resistive element 108 is for example a bipolar device programmable by the polarity of the programming current passed through. For example, the element 108 is an OxRAM device (oxide RAM), a PCM device (phase change memory) or a MRAM device (magnetic RAM) based on the STT (spin transfer torque) technology.
    As mentioned above, the bidirectional selection device 110 is a non-linear bipolar device, which will let a current flow in one or the other direction when a voltage threshold Vt at its terminals is reached. Below the voltage threshold Vt, the device 110 for example passes a relatively low current. Thus, the selection device behaves for example as a bidirectional diode. For example, as known to those skilled in the art, such a bidirectional selection device can be formed, inter alia, by: a tunnel barrier device, a metal-insulator-metal (MIM) structure based on a Schottky emission; or a bidirectional threshold switching device induced by joule heating. For example, such devices are described in more detail in the publication by J. Woo et al., Entitled "Selector Devices for High Density Cross-point ReRAM", 14th Non-Volatile Memory Technology Symposium (NVMTS 2014) Oct 27th - 29th , 2014, Jeju, Korea, whose contents are considered included here within the limits allowed by law.
    Thus, when a voltage V> Vt is applied across the memory cell, the voltage drop Vr in the resistive element 108 will be equal to V-Vt. The threshold voltage Vt is for example chosen to be greater than Vsel / 2, so that it will pass a relatively weak current in the memory cells that are not selected in the matrix. In one embodiment, Vt is selected in the range of 0.8 to 1.5 V, and is for example equal to about IV. The voltage V is for example in the range of 1 to 3 V and is for example equal to approximately 2 V, and the voltage Vr at the terminals of the resistive element during a programming phase is in the range of 1 to 2 V, and for example around 1.4 V.
    FIG. 2 is a graph illustrating an example of the programming voltages and the resulting currents in the memory cell 106 of FIG. 1B according to an exemplary embodiment in which the resistive element 108 is implemented by an OxRAM device.
    As represented by a solid line curve, when the resistive element 108 is in the low resistive state, until the threshold voltage Vt or -Vt is reached, the current in the memory cell will be at a low level of Imin or less. In the example of FIG. 2, the positive and negative thresholds Vt, -Vt are of the same amplitude, but it would be possible in certain embodiments for these thresholds to have different amplitudes. When the voltage is greater than Vt or less than -Vt, the current is proportional to V-Vt. However, if a negative level Voff is reached, the resistive element will switch to the high resistive state, and the current will fall to a relatively low level.
    As represented by a broken line curve, when the resistive element 108 is in the high resistive state and the voltage across the memory cell passes above Vt and reaches a Von level, the current rises sharply when the resistive element switches to the low resistive state. The current increases until a certain current limit reaches it. The level of this current limit determines the resistance of the resistive element in the low resistive state.
    In the case of other types of resistive elements, the behavior of the device when the voltage Von is reached may be different. For example, in memory cells based on MRAM technologies, the current limit does not adjust the resistance level of the low resistive state, but determines the retention time. In another example, in PCM (phase change memory) technologies, the current limit determines the volume of material that is programmed, and thus has an impact on the resistance of the device. Note that PCM devices are programmed unipolar, which means that it is not the direction of the programming current, but the current level, which determines the programmed resistance.
    It is therefore advantageous to limit the current, with a relatively high accuracy, to a desired current limit Ilimit to control the resistive properties of the resistive element.
    Figure 3 illustrates a memory device 300 including the memory array. non-volatile intersection point 100 of Figure IA and comprising circuits for limiting the programming current according to an exemplary embodiment. As has been mentioned in connection with FIG. 1A, while the memory array comprises only four rows and four columns of memory cells, in alternative embodiments it could comprise any number n of rows and any number m of columns.
    A selected row current limiting circuit (SELECTED ROW CURRENT LIMITER) 302 is for example coupled to the selected row conductor track, and is adapted to apply a selected conductive track voltage level Vsel to that row conductor track. In addition, the circuit 302 is adapted to limit the current supplied to this row conductor track. The other row-conducting tracks are for example coupled to an unselected conductive track voltage Vusel, which corresponds for example to the voltage Vx of FIG. 1A, by a row control circuit (not shown in the figures).
    A column selection circuit (not shown in the figures) is for example adapted to couple the selected one of the column conductor tracks to the voltage Vb. For example, an unselected column select circuit (UNSELECTED COL SELECTION) 304 is adapted to apply the unselected conductive track voltage Vusel to each of the unselected column conductor tracks. Thus, in the example of FIG. 3, the same voltage is applied for example to non-selected row conductive tracks and unselected column conductive tracks. In some embodiments, the voltage Vb is 0 V, and the Vusel voltage is approximately Vsel / 2. However, depending on the Vsel level, the voltage Vsel / 2 may not be high enough to correctly polarize transistors in the circuit 304. In such a case, the voltage Vb may be chosen so as to be positive, for example equal to at about 0.5 V, and the other voltages shifted accordingly. Thus, for example, rather than being equal to Vsel / 2, the voltage Vusel is for example equal to Vb + (Vsel-vB) / 2.
    The circuit 304 is also for example adapted to generate a sum T, Ileak leak currents on unselected column conductive tracks.
    In the example of Figure 3, the second memory cell from the top and second from the left is selected.
    A programming current reference circuit (PROG CURRENT REF) 306 is for example adapted to generate a reference current Iref corresponding to a desired programming current limit Iiimit of the memory cell to be programmed. An adder 308 is for example adapted to add the reference current Iref to the sum Σ, Ιιεακ leakage currents to generate a current limit Ie · This current limit 1 ^ is supplied to the selected row current limiting circuit 302 , and is used by this circuit to limit the current in the selected row conductor track.
    In some embodiments, the programmable resistive element of each memory cell is an element, such as an OxRAM element, having a low resistance state that depends on the level reached by the programming current during the programming phase. In such a case, the memory device is for example capable of programming each resistive element so as to take one of a plurality of low resistive states, which allows each element to store more than one data bit. . This is achieved, for example, by setting, during each programming phase, an appropriate value of the reference current IreF among a plurality of selectable levels such that the programming current is limited to a level corresponding to a desired low resistance state. For example, in one embodiment, there are three separate programming streams for programming three distinct low resistance states (LRS), and one high resistance state (HRS). Thus, there are a total of four distinct resistive states, which makes it possible to store two bits of data in each programmable resistive element.
    Although in the example of FIG. 3, the current limit Ir is imposed by the circuit that supplies the supply voltage Vsel, in alternative embodiments, the current limit could be imposed by the circuit that supplies the voltage. Vb supply, as will now be described with reference to Figure 4.
    FIG. 4 schematically illustrates a non-volatile memory circuit 400 according to an alternative embodiment with respect to FIG. 3. As illustrated, the column control circuit (not illustrated in the figures) is adapted to couple a conductive track of column selected at a voltage Vsel rather than the voltage Vb. In addition, the circuit 302 is replaced by a selected row current limiting circuit 402 adapted to apply a voltage Vb to the selected row conductor track, and to limit the current to a value Ir in a manner similar to the circuit 302.
    Fig. 5 is a flowchart illustrating steps in a programming current limiting method in a nonvolatile point-of-intersection memory array, such as the matrix 100 of Fig. 1A.
    In a step 501, a row conductive track and a column conductive track of a memory cell to be programmed are selected. For example, the selected row conductor track is coupled to the voltage level Vsel, and the selected column conductor track is coupled to the voltage Vb, or vice versa. This triggers the start of the programming phase.
    In the following step 502, the current supplied to the selected row conductor track is limited on the basis of a current limit II. In particular, step 502 comprises for example the following substeps 502A through 502C, which are all for example performed continuously during the programming phase of the memory cell.
    In step 502A, the leakage current on the unselected column conducting tracks during the programming phase is detected and summed to generate the sum Σ Ileak · The sum Σ, Ιιεακ is for example represented by a current level, although that in alternative embodiments it can be represented by a voltage level.
    In step 502B, the current limit II is generated on the basis of the sum of the leakage currents and the reference programming current Iref · Here again, the current limit Il is for example represented by a current level, although in alternative embodiments it may be represented by a voltage level.
    In step 502C, the current supplied to the selected row conductor track during the programming phase is limited based on the current limit.
    After step 502, a step 503 is performed, during which it is determined whether the end of the programming phase has been reached. For example, in some embodiments, this involves determining whether the current limit II 3 has been reached, and if so, the voltage Vsel is no longer applied to the selected row or column conductive track, thereby terminating the phase. programming. In the other case, the programming phase always continues for a certain time. If the programming phase has not yet ended, step 502 continues. Once the end of the programming phase is reached, the process ends at step 504.
    Figure 6 schematically illustrates the memory device 300 of Figure 3 in more detail according to an exemplary embodiment. The manner in which the implementation of FIG. 6 could be adapted to implement the memory device 400 of FIG. 4 will be readily apparent to those skilled in the art.
    The unselected column selection circuit 304 includes, for example, a line 602 coupled to each of the unselected column conductor tracks. For example, the line 602 is coupled to each of the column conducting tracks, denoted Cg to (¾ in FIG. 6, via a corresponding selection NMOS transistor Tg to Tjyj, controlled by a corresponding control signal Sg to For example, the totality of the control signals Sg is activated during a programming phase, except for the signal corresponding to the selected column conductor track.The line 602 provides the sum of the leakage currents Σ Ileak.
    The Vusel voltage is for example applied to each of the non-selected column conducting tracks of the conductive tracks Cg to (¾ by a voltage regulator formed by an NMOS transistor 604 having one of its main conduction nodes coupled to the line 602 and having its control node controlled by a comparator 606, which is for example implemented by an operational amplifier The comparator 606 has one of its inputs coupled to the line 602, and its other input coupled to the voltage level Vusel , which is for example at or near Vsel / 2. The other main conduction node of the transistor 604 is coupled to an output line of the circuit 304 supplying the sum of leak currents YiIleak, and is for example coupled to the ground rail via an NMOS transistor 610. The adder 308 is for example implemented by a pair of current mirrors A first current mirror is formed by the tr ansistor 610 and another NMOS transistor 612 coupled between an output line 614 of the adder and the ground rail. The control nodes of the transistors 610, 612 are coupled to each other and to the drain of the transistor 610, so that the transistor 610 forms the reference branch of the current mirror, and the transistor 612 passes a current based on the current Y The other current mirror is formed by an NMOS transistor 616 coupled between the programming current reference circuit 306 and the ground rail, and an NMOS transistor 618 coupled between the line 614 and the ground rail. The circuit 306 comprises, for example, a current source 619 coupled between the transistor 616 and a supply voltage rail VDDH, the current source 619 supplying the reference current Iref and the adder 308. The control nodes of the transistors 616 , 618 are coupled to each other and to the drain of transistor 616, so that transistor 616 forms the reference branch of the current mirror, and transistor 618 passes a current based on reference current IreF ·
    In some embodiments, the transistors 612 and 618 have the same dimensions as the transistors 610 and 616, so that the transistor 612 passes the T.Ileak current and the transistor 618 passes the current Iref · However, in variants it would be possible for these transistors to have different dimensions so that the IREF and Σ leak currents are increased or decreased by the same factor.
    The sum of the currents driven by the transistors 612 and 618 provides the current limit II on the line 614, which is supplied to the selected row current limiting circuit 302.
    The circuit 302 comprises for example a first current mirror consisting of PMOS transistors 620 and 622 each having their source coupled to the supply voltage rail VDDH. The control nodes of the transistors 620 and 622 are coupled to each other and to the drain of the transistor 620, so that the transistor 620 forms the reference branch of the current mirror. The drain of the transistor 622 is for example coupled to a node 624, which is in turn coupled to the ground rail via a resistor 626. The node 624 provides a voltage Vl based on the current I - ^, and is coupled to a first input of a comparator 628, which is for example implemented by an operational amplifier.
    The comparator 628 compares the voltage Vl to a feedback voltage Vpg. The feedback voltage Vpg is provided by a node 630 coupled to the ground rail through a resistor 631. A current flowing through the resistor 631 is provided by a current mirror formed by a PMOS transistor 632 coupled in series with the resistor 631, and a PMOS transistor 634. The transistors 632, 634 have their sources coupled to the supply rail VDDH, and their control nodes coupled to each other and to the drain of the transistor 634, so that the transistor 634 forms a branch reference of the current mirror. The drain of transistor 634 is coupled to the selected row conductor track (SELECTED WL), denoted 636 in FIG. 6, through an NMOS transistor 638. Transistor 638 forms a voltage regulator for applying voltage Vsel to the selected row conductor track. For example, the control node of the transistor 638 is coupled to the output of a comparator 640, which is for example implemented by an operational amplifier, and which has its negative input coupled to the selected row conductor track 636, and its positive input coupled to the output of a multiplexer 642. An input of the multiplexer 642 receives the voltage level Vsel, and the other input of the multiplexer 642 is for example coupled to ground, or Vusel. The multiplexer 642 is controlled by the output signal S_OUT of the comparator 628.
    In operation, at the beginning of the programming phase of the selected memory cell, the signal S_OUT on the output of the comparator 628 is for example low, and thus controls the multiplexer 642 to supply the voltage Vsel to the comparator 640. The row conductive track selected 638 is thus brought to the voltage Vsel, and the programming current will start to rise. During the programming phase, the circuits 304, 306 and 308 generate the current limit II · The circuit 302 converts the current limit II to a voltage level Vl, and uses the current mirror formed by the transistors 632 and 634 , and resistor 631, to generate the feedback voltage Vpg based on the current IWL level on the selected row conductor track 636. These voltages and Vp are compared by the comparator 628. When the current IWL on the conductive trace of selected row reaches the current limit II, the output signal S_OUT of the comparator 628 for example goes high, causing the multiplexer 642 to couple the input of the comparator to the ground or to another low level, so that the programming current is stopped or reduced significantly.
    All the transistors in the circuit of FIG. 6 are, for example, N-channel MOS transistors (NMOS) or P-channel MOS transistors (PMOS), and it will be apparent to those skilled in the art that variants, one or more of the PMOS transistors could be replaced by NMOS transistors, and vice versa. For example, the NMOS transistors 604 and 638 could be replaced by PMOS transistors, and in such a case, the positive and negative inputs of the corresponding comparators 606, 640 are also inverted.
    FIG. 7 illustrates the memory device of FIG. 3 according to an alternative embodiment with respect to FIG. 6. Many elements of the circuit of FIG. 7 are identical to elements of the circuit of FIG. 6, and these elements carry the same references and will not be described again in detail.
    The circuits 304, 306 and 308 of FIG. 7 are for example implemented in the same manner as in FIG. 6, and these circuits will not be described again. The circuit 302 is, however, modified to remove the comparator 628 and the multiplexer 642. Instead, the current limit II is applied to the reference branch of a current mirror formed by PMOS transistors 702 and 704 having their nodes. control coupled to each other and to the drain of the transistor 702. The transistor 702 is coupled between the line 614 and the power supply rail VDDH, and the transistor 704 is coupled in series with the transistor 638. The comparator 640 receives, on its negative input , the voltage level Vsel.
    Thus, in the embodiment of FIG. 7, the current IWL on the selected row conductor track 636 is directly limited by the current mirror formed by transistors 702 and 704. In operation, at the beginning of the programming phase, the current IWL will be lower than the current II, and will start to rise, but as soon as it reaches the limit of current II, it will not go up.
    There is, for example, no detection of the end of the write phase in the circuit of FIG. 7. As a variant, although this is not shown in FIG. 7, it would be possible to couple the positive input of FIG. comparator 640 at the output of a multiplexer 642 as in FIG. 6, with one input of the multiplexer 642 coupled to Vsel, and the other to the ground or voltage Vusel. In such a case, rather than being controlled by the comparator 628 (not present in Figure 7), the multiplexer 642 could for example be controlled by an inverter having its input connected to the line 636. Before the current limit IL has not been reached, the voltage on the line 636 will be relatively high, and the inverter will provide a low voltage controlling the multiplexer 642 to supply the voltage Vsel to the comparator 640. However, when the current limit II is reached, the voltage on line 636 will drop, and the output of the inverter will go high, controlling multiplexer 642 to provide the ground voltage or other low voltage to comparator 640.
    In the embodiments of Figures 3 and 4, a single memory cell of the array is selected and programmed during each programming phase. In alternative embodiments, several memory cells of a given column could be selected and programmed at the same time, as will now be described with reference to FIG. 8.
    FIG. 8 diagrammatically illustrates a memory device 800 according to another exemplary embodiment, comprising the same memory matrix 100 as in FIG.
    The memory device 800 includes a selected first row current limiter circuit (SELECTED ROW 1 CURRENT LIMITER) 804-1 coupled to a selected first row 1 of the memory array. The memory device also includes one or more other current limiting circuits, up to a k-th circuit (SELECTED ROW k CURRENT LIMITER) 804-k, respectively coupled to one or more other selected rows of the memory array.
    A single selected column conductor track is for example coupled to the voltage Vj-j, and the other column conductor tracks are coupled to the unselected column selection circuit 304. Since more than one of the rows receives a programming current , the output of the circuit 304 is a current Σ, ^ Σ, ^ εακ equal to the sum of the leakage currents generated by the k programming currents. This current is for example supplied to a circuit 806, which divides the current by k, in order to generate a selected average leakage current per row. The result of the division is for example supplied to an adder 808, which adds it to the reference current Iref supplied by the circuit 306, and provides a current limit 1, which is supplied to each of the circuits 804-1 through 804. -k.
    Of course, in alternative embodiments, the circuits 804-1 through 804-k could supply the voltage Vjq to selected row conductor tracks rather than the Vsel voltage, and a column select circuit (not shown in FIG. 8). , could apply the voltage to the selected column conductor track.
    Figure 9 schematically illustrates the memory device 800 of Figure 8 in more detail according to an exemplary embodiment.
    The circuits 304 and 306 are for example the same as these circuits in FIG. 6 and will not be described again in detail.
    The circuits 806 and 808 for dividing the current ΕλΣ / ιελκ by k and for adding the result to the current Iref are for example implemented by a circuit similar to the circuit of the adder 308 of FIG. 6. However, the transistors 610 and 612 of the current mirror receiving current T.ILeak are replaced by transistors 902 and 904 respectively. The widths of the transistors 902 and 904 are for example different in order to implement the division function of the circuit 806. For example, by calling W the width of the transistor 902, the width of the transistor 904 is for example W / k.
    The current limiting circuits 804-1 to 804-k are each, for example, implemented by a circuit similar to the circuit 302 of FIG. 7, except that the transistor 702 is for example implemented in only one of these circuits, for example in circuit 804-1, and each of circuits 804-1 through 804-k includes transistor 704-1 through 704-k respectively having its gate coupled to line 614 to limit current on the row conductor track At least one of the circuits 804-1 through 804-k includes a corresponding transistor 638-1 through 638-k and a corresponding multiplexer 640-1 through 640-k coupled to the corresponding selected row conductor track IWL. ^ IWL.
    An advantage of the embodiments described herein is that the leakage currents in an intersection point memory array can be compensated for in a simple and accurate manner.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art. For example it will be apparent to those skilled in the art that although a circuit comprising MOS transistors has been described, in alternative embodiments, different transistor technologies, such as bipolar technology, could be used.
    In addition, it will be clear to those skilled in the art that the level of the VDDH supply voltage will depend on the particular technology used for the resistive element, and that rather than the circuits be coupled to a ground voltage. they could be coupled to a different voltage level, which could be negative.
    权利要求:
    Claims (12)
    [1" id="c-fr-0001]
    A memory device comprising: an intersection point memory array (100) comprising a plurality of row conductive tracks (102), a plurality of column conductive tracks (104) and a plurality of memory cells (106) arranged in rows and columns, each memory cell (106) comprising a nonvolatile programmable resistive element (108) coupled between a corresponding one of the row conductive tracks and a corresponding one of the column conductive tracks; a power supply circuit (302, 402) adapted to supply a programming current (IWL) to a selected one of the row conductor tracks during a programming operation to change the resistive state of a coupled selected memory cell between the selected row conductor track and a selected one of the column conductor tracks; a leakage current detection circuit (304) coupled to the plurality of column conductor tracks (104) except for the selected column conductor track adapted to detect leakage currents during the programming operation; and a current limit generating circuit (308) adapted to generate a current limit (II) based on the sum of the leakage currents and a reference current (Iref) / and to provide the current limit to the power supply circuit (302) for limiting the programming current.
    [2" id="c-fr-0002]
    Memory device according to claim 1, wherein the current limit generating circuit (308) is adapted to generate the current limit (II) by adding the sum of the leakage currents to the referenced current (Iref)> in wherein the reference current represents the programming current to be applied to the selected memory cell.
    [3" id="c-fr-0003]
    The memory device according to claim 1 or 2, wherein the power supply circuit (302) comprises a voltage regulator (638, 640) for controlling a first voltage level (Vsel) applied to the row conductor track. selected.
    [4" id="c-fr-0004]
    The memory device according to claim 3, wherein the voltage regulator (638, 640) comprises a first transistor (638) coupled to the selected row conductor track and having its control node coupled to the output of a comparator ( 640) adapted to compare the voltage on the selected row conductor track with a reference voltage equal to the first voltage level (Vsel).
    [5" id="c-fr-0005]
    A memory device according to any one of claims 1 to 4, wherein the power supply circuit (302) comprises a current mirror (702, 704) having a reference branch (702) coupled to receive the current limit (¾) and another branch (704) coupled to the selected row conductor track.
    [6" id="c-fr-0006]
    The memory device according to any one of claims 1 to 4, wherein the current supply circuit (302) comprises another comparator (628) adapted to compare a first voltage level (Vl) generated on the basis of the current limit (II) at a second voltage level (Vpg) generated on the basis of the programming current, and controlling the programming current on the basis of the comparison.
    [7" id="c-fr-0007]
    The memory device according to any one of claims 1 to 6, wherein the leakage current detecting circuit (304) comprises a voltage regulator (604, 606) for controlling a second voltage level (Vusel) applied to column conducting tracks (104) except at the selected column conducting track.
    [8" id="c-fr-0008]
    The memory device according to any one of claims 1 to 7, wherein the current limit generating circuit (308) comprises: a first current mirror (610, 612) having a reference branch (610) coupled with to receive the sum of the leakage currents, and another branch (612); a second current mirror having a reference branch (616) coupled to receive the reference current (Iref), and another branch (618), the other branches (612, 618) of the first and second current mirrors being coupled to an output line (614) of the current limit generating circuit (308) providing the current limit (II).
    [9" id="c-fr-0009]
    The memory device according to any one of claims 1 to 8, comprising: one or more other power supply circuits (804-k) adapted to supply a programming current (IWLfc) to one or more other conductive paths of row selected during the programming operation to change the resistive state of one or more of the memory cells coupled to the selected column conductor track; and a dividing circuit (806) adapted to divide the sum of the leakage currents by the number of current supply circuits.
    [10" id="c-fr-0010]
    The memory device of any one of claims 1 to 9, wherein the nonvolatile programmable resistive element (108) is one of the following: an OxRAM (random access memory oxide) device; a PCM (phase change memory) device; and an MRAM device (magnetic RAM).
    [11" id="c-fr-0011]
    The memory device according to any one of claims 1 to 10, wherein each memory cell further comprises a bidirectional selection device (110) coupled in series with the nonvolatile programmable resistive element and adapted to drive over the a voltage threshold (Vt).
    [12" id="c-fr-0012]
    A method for limiting programming current ion in an intersection point nonvolatile memory array (100) comprising a plurality of row conductive tracks (102), a plurality of column conductor tracks (104), and a plurality of memory cells (106) arranged in rows and columns, each memory cell (106) comprising a nonvolatile programmable resistive element (108) coupled between a corresponding one of the row conductive tracks and a corresponding one of the column conductive tracks, the method comprising: providing, by a power supply circuit (302), a programming current (IWL) to one of the row conductor tracks during a programming operation to change the resistive state of a cell selected memory coupled between the selected row conductive track and one of the column conductive tracks; detecting, by a leakage current detection circuit (304) coupled to the plurality of column conductor tracks (104) except for the selected column conductor track, leakage currents during the programming operation; generating, by a current limit generating circuit (308), a current limit (1 ^) based on the sum of the leakage currents and a reference current (Iref); and supplying the current limit (II) to the power supply circuit (302) to limit the programming current.
    类似技术:
    公开号 | 公开日 | 专利标题
    US8416604B2|2013-04-09|Method of implementing memristor-based multilevel memory using reference resistor array
    US9224464B2|2015-12-29|Memory circuit and related method
    EP2833364A2|2015-02-04|Non-volatile magnetic three electrodes memory cell and associated array
    EP3154061B1|2018-11-14|Method and circuit for controlling the programming current in a non-volatile memory array
    US10748613B2|2020-08-18|Memory sense amplifiers and memory verification methods
    EP3227889A1|2017-10-11|Reading circuit for resistive memory
    FR2970590A1|2012-07-20|VOLATILE / NON VOLATILE MEMORY CELL WITHOUT CHARGE
    EP0544568B1|1994-08-10|Reading circuit for redundancy fuse for integrated memory
    US10395730B2|2019-08-27|Non-volatile memory device with variable readout reference
    FR2799874A1|2001-04-20|Semiconductor memory device, for use in read-only memory type units.
    FR2970589A1|2012-07-20|VOLATILE MEMORY CELL / NON VOLATILE
    FR2976711A1|2012-12-21|MEMORY CELL WITH VOLATILE AND NON-VOLATILE MEMORIZATION
    EP2987168B1|2019-03-13|Memory cell with non-volatile data storage
    FR2714202A1|1995-06-23|Integrated circuit memory with improved read time.
    US20200226073A1|2020-07-16|Random code generator with non-volatile memory
    US10297316B2|2019-05-21|Phase change memory apparatus and read control method to reduce read disturb and sneak current phenomena
    FR3089037A1|2020-05-29|NEURONAL CIRCUIT CAPABLE OF IMPLEMENTING SYNAPTIC LEARNING
    FR2786910A1|2000-06-09|Multilevel floating gate memory cell for ROM units, comprising current comparator, polarization voltage generator, transistor and decoder
    EP2987167B1|2019-03-06|Non-volatile memory cell
    KR102324591B1|2021-11-12|Memory sense amplifier with precharge
    EP3239983B1|2019-09-11|Unipolar resistive memory
    EP0845783A1|1998-06-03|Read circuit for memory
    FR3035998A1|2016-11-11|NON-VOLATILE MEMORY WITH PROGRAMMING CIRCUIT
    同族专利:
    公开号 | 公开日
    EP3154061A1|2017-04-12|
    FR3042304B1|2017-11-24|
    US20170103788A1|2017-04-13|
    US9666243B2|2017-05-30|
    EP3154061B1|2018-11-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20130114327A1|2011-05-31|2013-05-09|Yuichiro Ikeda|Variable resistance nonvolatile memory device|
    US20130148406A1|2011-07-21|2013-06-13|Kazuhiko Shimakawa|Nonvolatile semiconductor memory device and read method for the same|
    US20140112056A1|2011-12-01|2014-04-24|Panasonic Corporation|Nonvolatile semiconductor memory device and write method for the same|
    US7372753B1|2006-10-19|2008-05-13|Unity Semiconductor Corporation|Two-cycle sensing in a two-terminal memory array having leakage current|
    US8866121B2|2011-07-29|2014-10-21|Sandisk 3D Llc|Current-limiting layer and a current-reducing layer in a memory device|KR20190022984A|2017-08-24|2019-03-07|삼성전자주식회사|Memory device configured to prevent read failure due to leakage current into bit line and method of opeerating the same|
    US10157671B1|2017-09-12|2018-12-18|Macronix International Co., Ltd.|Fast switching 3D cross-point array|
    CN109946339A|2019-03-25|2019-06-28|天津七所高科技有限公司|A kind of matrix form far infrared electric current detecting method|
    法律状态:
    2016-10-28| PLFP| Fee payment|Year of fee payment: 2 |
    2017-04-14| PLSC| Search report ready|Effective date: 20170414 |
    2017-10-31| PLFP| Fee payment|Year of fee payment: 3 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1559648A|FR3042304B1|2015-10-09|2015-10-09|METHOD AND CIRCUIT FOR CONTROLLING PROGRAMMING CURRENT IN NON-VOLATILE MEMORY MATRIX|FR1559648A| FR3042304B1|2015-10-09|2015-10-09|METHOD AND CIRCUIT FOR CONTROLLING PROGRAMMING CURRENT IN NON-VOLATILE MEMORY MATRIX|
    EP16192626.6A| EP3154061B1|2015-10-09|2016-10-06|Method and circuit for controlling the programming current in a non-volatile memory array|
    US15/288,341| US9666243B2|2015-10-09|2016-10-07|Method and circuit for controlling programming current in a non-volatile memory array|
    [返回顶部]